The present invention relates to circuits for providing a logical output signal in accordance with crossing points of differential signals. Circuits of that kind can be advantageously used, for example, at a front end of an automatic test equipment (ATE). In such ATE environment, output signals of the devices under test (DUT) may be single-ended as well as differential type signals.
The value of an ATE for the user is dependent on many different factors. Two of them are universality in the meaning of how many different parts and/or different signal types can be tested, and performance in the meaning of speed and accuracy of gaining the testing results.
Regarding the circuits which are supposed to receive DUT generated signals, a problem occurs if DUTs which have single-ended signals (signals which need only one pin for exit to the ATE) should be tested on the same testing equipment as DUTs which provide differential signals (signals which need two pins where one pin represents the normal logic output level and the other pin represents the complementary logic output level).
For a clear understanding of the following drawings and description of the invention it is advisable to set forth the conventions used below.
FIG. 1a shows a basic circuit drawing of a comparator as used e.g. in ATE systems. It is essentially a symmetrical differential amplifier formed of transistors Q1 and Q2. This simple symmetrical differential amplifier basically provides two output signals: a normal and a complementary signal.
The input signal IN to Q1 is compared with a threshold value TH applied to Q2. The result is a normal signal OUT1 developed from Q2, and a complementary signal NOUT1 from Q1. Since both physical signals represent the same information content (a logical 0 means always that OUT1=low and NOUT1=high) it is sufficient and mostly used in symbolic representations and block diagrams to show, as depicted in FIGS. 1b and 1c, only one output line OUT instead of OUT1 and OUT2. The line OUT quite commonly represents the polarity of the normal signal and accordingly always behaves like OUT1.
Most of the present ATEs can only operate on single-ended signals and up to now only a few can handle differential signals. Currently used concepts for handling differential signals by single-ended ATEs are using two single-ended comparators C1 and C2, as shown in FIG. 2, where the threshold voltages VTH1 for C1 and VTH2 for C2 are set to the same level, usually 50% of the logic levels. In this example, SIG represents the input signal from the DUT to the ATE having the normal signal level and NSIG the complementary level.
A major disadvantage of this concept is the timing inaccuracy that occurs when the zero crossing point of the signals SIGxe2x88x92NSIG is not at the same zero crossing point of (SIGxe2x88x92VTH) and/or (NSIGxe2x88x92VTH).
Timing errors which result from even minimally delayed zero crossings are represented in FIG. 3, which shows that the output signals OUT1 of C1 and OUT2 of C2 are out of phase. The leading and trailing edges of both, OUT1 and OUT2, are shifted compared to the correct point in time, represented by the vertical dash line in the middle between the outer dash lines. The calculated signal curve (SIGxe2x88x92NSIG) shows the real signal crossing of SIG and NSIG. Derived from that curve, an expected timing-error free output signal OUT1_EXP is also represented in FIG. 3. The real zero crossings of NSIG/VTH and of SIG/VTH represent the outer dash lines, and they show at the bottom line of this figure the timing errors of OUT1 and OUT2 versus the real zero crossing of (SIGxe2x88x92NSIG). From this it is clear that further processing of inaccurate DUT signals by an ATE leads to measurement errors which in most cases can not result in a reliable estimation of the tested DUT.
It is noted that the shown phase shift is just one example of a situation where the crossing point between signals SIG and NSIG are not at the middle between the high and low level. Other situations can be, for example, different swings, levels, or transition times.
Therefore, different approaches have been discussed, which are shown in FIGS. 4a-4c. Some ATEs with the capability of handling both alternatives may use two single-ended comparators C1, C2 and one differential comparator D having a separate output line OUTD. The input line of the differential comparator D for the normal signal level is connected to the line carrying the differential signals SIG with the normal logic level at the input of C1, and the input line of D for the complementary signal level is connected to the line with the differential signals NSIG at the input of C2. The implementation of FIG. 4a suffers from the fact that there is an extra line required for the differential comparator output OUTD.
In order to reduce the output line expenditure, it is shown in the example of FIG. 4b that OUTD can be replaced by OUT1, however, by adding a switch SW1 which connects OUT1 either to the output of C1 or to the output of D, so that lines originally used for single-ended applications now serve differential applications.
FIG. 4c shows another alternative, where a switch SW2 can be used to route either one threshold voltage VTH1(2) or the complement signal NSIG (normal signal SIG) to one of the comparators C1(C2), dependent on whether SW2 is inserted into the VTH1 line to C1 or the VTH2 line to C2. FIG. 4c further shows the circuit modifications for C1: SW2 is only connected to C1, so that when in the single-ended mode SW2 connects C1 to threshold voltage VTH1, and when in differential mode SW2 connects C1 to NSIG at the input of C2.
The approaches according to FIGS. 4a and 4b have significant disadvantages in that each incoming signal line is loaded by an additional comparator that is not used when single-ended applications are run by the ATE. In these cases the differential comparator D represents a parasitic load. On the other hand, when the ATE is running differential applications the single-ended comparators C1 and C2 contribute to parasitic signal distortions. This has a negative impact on the ATE performance, because any incoming signal is delayed and frequency-limited due to parasitic capacitances on the input lines of the comparators. As a further disadvantage the fact can be regarded that the above-described approaches need considerably more electrical power and more silicon space for implementation. Furthermore, the solution shown in FIG. 4c is not useful for high-speed applications, because signals transferred via switches become distorted per se and provide signal delays and other distortions by themselves.
These above problems, however, can be solved by using two different dedicated ATEs or one ATE with different, dedicated plug-in printed circuit cards with pin dedicated electronic circuitry. Both solutions, however, again have severe disadvantages, like higher cost, extra floor space, and restrictions in universality of channel usage by the ATE.
It is an object of the invention to provide an improved circuit for providing a logical output signal in accordance with crossing points of differential signals.
These objects of the invention are solved by the independent claims. Preferred embodiments are shown by the dependent claims.
The circuit structure of the invention thus allows that two single-ended comparators are combined to a differential comparator without adding parasitic components to the measurement node of an ATE to which it is connected and therefore without causing a negative impact on the bandwidth of the ATE""s input channels. The number of additional components needed for the combining circuitry of the comparators as well as the additional current can also be minimal.
It is clear that the invention can be partly or entirely realized by suitable software subroutines or programs, which can be executed by a suitable data processing unit incorporated e.g. in the ATE controller circuitry.
It is also apparent that although described herein for the example of ATE applications, the invention is not limited thereto but can be applied wherever logical output signals in accordance with crossing points of different signals have to be provided.